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Data Sheet
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
June 1997
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.1
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Features: Single 5.0-Volt Read and Write Operations CMOS SuperFlash EEPROM Technology Endurance: 100,000 Cycles (typical) Greater than 100 years Data Retention Low Power Consumption: Active Current: 20 mA (typical) Standby Current: 10 A (typical) Fast Page-Write Operation 128 Bytes per Page, 512 Pages Page-Write Cycle: 5 ms (typical) Complete Memory Rewrite: 2.5 sec (typical) Effective Byte-write Cycle Time:39 s (typical) Fast Access Time: 70, 90, and 120 ns Latched Address and Data Automatic Write Timing with Internal Vpp Generation End of Write Detection Toggle Bit Data# Polling Hardware and Software Data Protection TTL I/O Compatibility JEDEC Standard Byte-wide EEPROM Pinouts Packages Available 32-Pin TSOP 32-Lead PLCC 32 Pin Plastic DIP flexibility while lowering the cost for program, data, and configuration storage applic ations. To meet high density, surface mount requir e ments, the 29EE512 is offered in 32-pin TSOP and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 2A and 2B for pinouts. Device Operation The SST page mode EEPROM offers in-circuit electrical write capability. The 29EE512 does not require separate erase and program operations. The internally timed write cycle executes both erase and program transparently to the user. The 29EE512 has industry standard optional Software Data Protection, which SST recommends always to be enabled. The 29EE512 is compatible with industry standard EEPROM pinouts and functionality. Read The read operation of the 29EE512 is controlled by CE# and OE#, both have to be low for the sy stem to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high mi pedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3).
Product Description The 29EE512 is a 64K x 8 CMOS page mode EEPROM manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturabi lity compared with alternate approaches. The 29EE512 writes with a 5.0-volt-only power supply. Internal erase/program is transparent to the user. The 29EE512 conforms to JEDEC standard pi nouts for byte-wide memories. Featuring high performance page write, the 29EE512 provides a typical byte-write time of 39 sec. The entire memory, i.e., 64K bytes, can be written page by page in as little as 2.5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the 29EE512 has on-chip hardware and software data protection schemes. Designed, manufa ctured, and tested for a wide spectrum of applica tions, the 29EE512 is offered with a gua ranteed page-write endurance of 104 or 103 cycles. Data retention is rated at greater than 100 years. The 29EE512 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the 29EE512 significantly improves performance and reliability, while lowering power consumption, when compared with floppy disk or EPROM approaches. The 29EE512 improves
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.2
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Write The page write to the SST29EE512 should always use the JEDEC Standard Software Data Prote ction (SDP) 3-byte command sequence. The 29EE512 contains the optional JEDEC approved Software Data Protection scheme. SST reco mmends that SDP always be enabled, thus, the de scription of the write operations will be given using the SDP enabled format. The 3-byte SDP Enable and SDP Write commands are identical; there fore, any time a SDP Write command is issued, software data protection is automat ically assured. The first time the 3-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired page write, the entire device remains protected. For additional descriptions, please see the application notes on "The Proper Use of JEDEC Standard Software Data Protection" and "Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories" in this data book. The write operation consists of three steps. Step 1 is the three byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the 29EE512. Steps 1 and 2 use the same timing for both operations. Step 3 is an nternally i controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP 3-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the T BLCO timer after the rising edge of WE# or CE#, whichever occurs first. The write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 14 and 16 for flowcharts. The write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three byte load sequence that allows writing to the selected page and will leave the 29EE512 pr tected at the end of o the page write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle co nsists of the TBLCO timeout and the write timer op eration. During the write operation, the only valid reads are Data# Polling and Toggle Bit. The page-write operation allows the loading of up to 128 bytes of data into the page buffer of the 29EE512 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the page-write feature of 29EE512 allows the entire memory to be written in as little as 2.5 seconds. During the internal write c ycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each page-write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A 7 through A16. Any byte not loaded with user data will be written to FF. See Figures 4 and 5 for the page-write cycle ti ming diagrams. If after the completion of the 3-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (TBLC ) of 100 s, the 29EE512 will stay in the page load cycle. Add itional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (T BLCO ) from the last byteload cycle, i.e., no subsequent WE# or CE# high-tolow transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. The page to be loaded is determined by the page address of the last byte loaded. Software Chip-Erase The 29EE512 provides a chip-erase operation, which allows the user to simultaneously clear the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six byte-load sequence. After the load sequence, the device enters into an internally timed cycle similar to the write cycle. During the erase operation, the only valid read is Toggle Bit.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.3
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flo wchart. Write Operation Status Detection The 29EE512 provides two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the ni ternal write cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simult a neous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ 7) When the 29EE512 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the co mplement of the true data. Once the write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. Toggle Bit (DQ 6) During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e., toggling between 0 and 1. When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a "1". Data Protection The 29EE512 provides both hardware and soft ware features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VCC Power Up/Down Detection The write opera: tion is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the write operation. This pr e vents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The 29EE512 provides the JEDEC approved o ptional software data protection scheme for all data alteration operations, i.e., write and chip erase. With this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the write c ycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. The 29EE512 is shipped with the software data protection di abled. s The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a sixbyte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 s. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts. The 29EE512 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single page write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled. Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Prote c-
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.4
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
tion (SDP) always be enabled. The 29EE512 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing. Please refer to the following Application Notes located at the back of this databook for more ni formation on using SDP: * * Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories The Proper Use of JEDEC Standard Software Data Protection hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations. Product Identification Table Byte Data Manufacturers Code 0000 H BF H Device Code 0001 H 5D H Product Identification Mode Exit In order to return to the standard read mode, the Software Product Identification mode must be e xited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the read operation. The reset oper tion a may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave a bnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 17 for a flo wchart. Table 1:
Product Identification The product identification mode identifies the d evice as the 29EE512 and manufacturer as SST. This mode may be accessed by hardware or soft ware operations. The hardware operation is typically used by a programmer to identify the co rrect algorithm for the SST 29EE512. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for
X-Decoder
524,288 Bit EEPROM Cell Array
A15 - A0
Address buffer & Latches Y-Decoder and Page Latches
CE# OE# WE#
Control Logic
I/O Buffers and Data Latches
DQ7 - DQ0
Figure 1:
Functional Block Diagram of SST 29EE512
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.5
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
A11 A9 A8 A13 A14 N/C WE# Vcc N/C N/C A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View
Die up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
Figure 2A:
Pin Assignments for 32-pin TSOP Pac kages
N/C N/C A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 23 22 21 20 19 18 17
Vcc WE# N/C A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 DQ1 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 4 A12
A15 N/C
N/C Vcc
WE# N/C
3
2
1
32 31 30 29 28 27 26 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-Pin PDIP
Top View 24
32-Lead PLCC Top View
25 24 23 22 21
14 15 16
17 18 19
20
DQ2
Vss DQ4 DQ6 DQ3 DQ5
Figure 2B:
Pin Assignments for 32-pin Plastic DIPs and 32-lead PLCCs
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.6
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Table 2: Symbol A15 -A7 A6-A0 DQ7-DQ0
Pin Description Pin Name Row Address Inputs Column Address Inputs Data Input/output
CE# OE# WE# Vcc Vss NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Functions To provide memory addresses. Row addresses define a page for a write cycle. Column Addresses are toggled to load page data. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the write operations To provide 5-volt supply ( 10%) Unconnected pins.
Table 3: Mode
Operation Modes Selection CE# OE# WE# VIL VIL VIH X X VIL VIL VIL VIH X VIL X VIH VIL VIH VIL X X VIH VIL VIH
DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN Manufacturer Code (BF) Device Code (5D)
Address AIN AIN X X X AIN , See Table 4 A15 - A1 = VIL, A9 = VH, A0 = VIL A15 - A1 = VIL, A9 = VH, A0= VIH See Table 4 See Table 4 See Table 4
Read Page Write Standby Write Inhibit Write Inhibit Software Chip Erase Product Identification Hardware Mode
Software Mode SDP Enable Mode SDP Disable Mode
VIL VIL VIL
VIH VIH VIH
VIL VIL VIL
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.7
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Table 4:
Command Sequence
Software Command Codes
1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr (1) Data Addr (1) Data Addr (1) Data Addr (1) Data Addr (1) Data Addr (1) Data 5555H AAH 2AAAH 55H 5555H A0H Addr(2) Data
Software Data Protect Enable & Page Write Software Data Protect Disable Software Chip Erase Software ID Entry Software ID Exit Alternate Software ID Entry(3)
5555H 5555H 5555H 5555H 5555H
AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H AAH 2AAAH 55H
5555H 5555H 5555H 5555H 5555H
80H 80H 90H F0H 80H
5555H 5555H
AAH 2AAAH 55H AAH 2AAAH 55H
5555H 5555H
20H 10H
5555H
AAH 2AAAH 55H
5555H
60H
Notes: (1) Address format A14 -A0 (Hex), Address A15 is a "Don't Care".
(2) (3) (4)
Page Write consists of loading up to 128 bytes (A - A0). 6 Alternate 6 byte Software Product ID Command Code The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part.
Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A = 0, 0 29EE512 Device Code = 5DH, is read with A = 1. 0 2. The device does not remain in Software Product ID Mode if powered down. 3. This product supports both the JEDEC standard 3 byte command code sequence and SST's original 6 byte command code sequence. For new designs, SST recommends that the 3 byte command code sequence be used.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.8
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Max imum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the perational sections o of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ........................................................................ Storage Temperature ............................................................................. D. C. Voltage on Any Pin to Ground Potential ........................................ Transient Voltage (<20 ns) on Any Pin to Ground Potential ................... Voltage on A9 Pin to Ground Potential .................................................... Package Power Dissipation Capability (Ta = 25C) ................................. Through Hole Lead Soldering Temperature (10 Seconds) ...................... Surface Mount Lead Soldering Temperature (3 Seconds) ...................... (1) Output Short Circuit Current ................................................................. -55C to +125C -65C to +150C -0.5V to VCC+ 0.5V -1.0V to VCC+ 1.0V -0.5V to 14.0V 1.0W 300C 240C 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range
Range Commercial Industrial Ambient Temp 0 C to +70 C -40 C to +85 C VCC 5V10% 5V10%
AC Conditions of Test
Input Rise/Fall Time...............10 ns Output Load...........................1 TTL Gate and CL = 100 pF See Figures 12 and 13
Table 5:
DC Operating Characteristics Min Limits Max 30 50 3 50 1 10 0.8 2.0 0.4 2.4 11.6 12.4 200 Units mA mA mA A A A V V V V V A Test Conditions CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. CE#=OE#=WE#=VIH, VCC =VCC Max. CE#=OE#=WE#=VCC -0.3V. VCC = VCC Max. VIN =GND to VCC, VCC = VCC Max. VOUT =GND to VCC, VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. IOL = 2.1 mA, VCC = VCC Min. IOH = -400A, VCC = VCC Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max.
Symbol Parameter ICC Power Supply Current Read Write Standby VCC Current (TTL input) Standby VCC Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A 9
ISB1 ISB2 ILI ILO VIL VIH VOL VOH VH IH
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.9
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Table 6: Power-up Timings Symbol Parameter (1) TPU-READ Power-up to Read Operation TPU-WRITE (1) Power-up to Write Operation
Maximum 100 5
Units s ms
Table 7: Capacitance (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition (1) I/O Pin Capacitance VI/O = 0V CI/O CIN
(1)
Maximum 12 pF 6 pF
Input Capacitance
(1)
VIN = 0v
Note:
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 8: Symbol NEND TDR
) (1)
Reliability Characteristics Parameter Minimum Specification Endurance 1,000 & 10,000(2) Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up 100 1000 200 100
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 MIL-STD-883, Method 1008 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 17
VZAP_HBM (1 VZAP_MM (1) ILTH (1)
(1)
Note:
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(2)
See Ordering Information for desired type.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.10
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
AC Characteristics Table 9: Symbol TRC TCE TAA TOE TCLZ (1) TOLZ (1) TCHZ (1) TOHZ (1) TOH (1) Read Cycle Timing Parameters 29EE512-70 Parameter Min Max Read Cycle Time 70 Chip Enable Access Time 70 Address Access Time 70 Output Enable Access Time 30 CE# Low to Active Output 0 OE# Low to Active Output 0 CE# High to High-Z Output 20 OE# High to High-Z Output 20 Output Hold from Address 0 Change 29EE512-90 Min Max 90 90 90 40 0 0 30 30 0 29EE512-120 Min Max 120 120 120 50 0 0 30 30 0
Units ns ns ns ns ns ns ns ns ns
Table 10: Symbol TWC TAS TAH TCS TCH TOES TOEH TCP TWP TDS TDH TBLC (1) TBLCO (1) TIDA TSCE Note:
(1)
Page-Write Cycle Timing Parameters Parameter Min Write Cycle (erase and program) Address Setup Time 0 Address Hold Time 50 WE# and CE# Setup Time 0 WE# and CE# Hold Time 0 OE# High Setup Time 0 OE# High Hold Time 0 CE# Pulse Width 70 WE# Pulse Width 70 Data Setup Time 35 Data Hold Time 0 Byte Load Cycle Time 0.05 Byte Load Cycle Time 200 Software ID Access and Exit Time Software Chip Erase
Max 10
100 10 20
Units ms ns ns ns ns ns ns ns ns ns ns s s s ms
This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.11
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Figure 3:
Read Cycle Timing Diagram
Figure 4:
WE# Controlled Page Write Cycle Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.12
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Figure 5:
CE# Controlled Page Write Cycle Timing Diagram
Figure 6:
Data# Polling Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.13
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Figure 7:
Toggle Bit Timing Diagram
Figure 8:
Software Data Protect Disable Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.14
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Figure 9:
Software Chip Erase Timing Diagram
Figure 10:
Software ID Entry and Read
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.15
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Figure 11:
Software ID Exit and Reset
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.16
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
2.4 INPUT
2.0 REFERENCE POINTS 0.8
2.0 OUTPUT 0.8
0.4
AC test inputs are driven at V (2.4 VTTL ) for a logic "1" and VOL (0.4 VTTL ) for a logic "0". Measurement OH reference points for inputs and outputs are V (2.0 VTTL ) and VIL (0.8 VTTL ). Inputs rise and fall times IH (10% 90%) are <10 ns. Figure 12: AC Input/Output Reference Waveforms
TEST LOAD EXAMPLE
VCC
TO TESTER
RL
HIGH
TO DUT
CL
RL
LOW
Figure 13:
Test Load Example
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.17
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Start
See Figure 16
S o ffttw a rr eDD aa a So wa e at t P r t t c t rite P r ooe etc WW rite Co man C o m m a n dd
Set Page Address
Set Byte Address = 0
Load Byte D a ta
Increm e n t Byte Address By 1
No
Byte Address = 128 ? Yes
W ait T B C O W a i t T B LLC O
W a ii t f o rr e n ddoo f W a t fo en f W r Werite W CW C , a t a i t ( T (T , D # T oo lg il n g ib io ro r Pgl e b t t D a t T o gP o l l i n g b i t a # g le bit o o p e r a ttiio nn ) ra o )
W rite C o m p leted Figure 14: Write Algorithm
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.18
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Data# Polling
Internal Timer
Toggle Bit
Page Write Initiated
Page Write Initiated
Page Write Initiated
Wait TWC
Read a byte from page
Read DQ7 (Data for last byte loaded)
Write Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Write Completed
Write Completed
Figure 15: Wait Options
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.19
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Software Data Protect Enable Command Sequence
Software Data Protect Disable Command Sequence
Write data: AA Address: 5555
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Write data: A0 Address: 5555
Write data: 80 Address: 5555
Load 0 to 128 Bytes of page data
Optional Page Load Operation
Write data: AA Address: 5555
Write data: 55 Address: 2AAA Wait TBLCO Write data: 20 Address: 5555 Wait TWC Wait TBLCO
SDP Enabled Wait TWC
SDP Disabled
Figure 16:
Software Data Protection Flowcharts
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.20
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Software Product ID Entry Command Sequence
Software Product ID Exit & Reset Command Sequence Write data: AA Address: 5555
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Write data: 90 Address: 5555
Write data: F0 Address: 5555
Pause 10 s
Pause 10 s
Read Software ID
Return to normal operation
Figure 17:
Software Product Command Flowcharts
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.21
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Software Chip-Erase Command Sequnce Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 80 Address: 5555
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 10 Address: 5555
Wait TSCE
Chip Erase to FFH
Figure 18:
Software Chip Erase Command Codes
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.22
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Product Ordering Information
Device SST29EE512 -
Speed XXX -
Suffix1 XX -
Suffix2 XX
Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up) U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles 4 = 10,000 cycles Read Access Speed 120 = 120 ns 90 = 90 ns 70 = 70 ns
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.23
SST 29EE512 5.0V-only 512 Kilobit Page Mode EEPROM
Valid combinations SST29EE512- 70-4C- EH SST29EE512- 90-4C- EH SST29EE512-120-4C- EH SST29EE512- 90-3C- EH SST29EE512-120-3C- EH SST29EE512- 90-4I-EH SST29EE512-120-4I-EH SST29EE512-120-3C-U1 SST29EE512-120-4C-U1
Example: Valid combinations are those products in m ass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part.
SST29EE512- 70-4C- NH SST29EE512- 90-4C- NH SST29EE512-120-4C- NH SST29EE512- 90-3C- NH SST29EE512-120-3C- NH SST29EE512- 90-4I-NH SST29EE512-120-4I-NH
SST29EE512- 70-4C- PH SST29EE512- 90-4C- PH SST29EE512-120-4C- PH SST29EE512- 90-3C- PH SST29EE512-120-3C- PH
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
2.24

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